Full Chip Physical Design Leader (1人)
| 职位编号： | THR000668 | 招聘职位： | Full Chip Physical Design Leader |
| 工作类型： | 全职 | 年薪： | 面议 |
| 要求性别： | 男 | 年龄要求： | 28 - 38 |
| 学历要求： | 本科及以上 | 工作地区： | 北京 |
| 工作经验： | 6年以上 | 户口要求： | |
| 发布日期： | 2018-06-11 | 有效期限： | 3个月 |
1、 This is a leadership job role for full chip physical design.
2、 Tasks include hierarchical full chip floorplan/partition work, power planning, bus planning, feedthrough, pin assignments, pipeline/repeater insertion,SOC clock planning, chip assembly, etc.
3、 Work with architecture/RTL design team, system/package team, block level physical design team to drive the achievement of optimum floorplan.
4、 Drive best of the knowledge methodology in all aspects of full chip implementation.
1、MSEE with 15+ years of experience in physical design in both full chip and block level work, CAD/methodology (familiar with AMD FCFP flow is a plus).
2、Solid understanding of full chip tasks and issues facing high performance(2~3GHZ range) and large SOC(300+ sqmm in 7nm).
3、Strong programming skills in Python/Perl/TCL
4、Padring/IO/bump planning, bump routing, ESD, multi-voltage experience is a plus.
5、TSMC 7nm experience is a big plus.
